1. Field of the Invention
The present invention relates to a non-volatile memory and fabricating method thereof. More particularly, the present invention relates to a flash memory cell and fabricating method thereof.
2. Description of the Related Art
Flash memory is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. The stored data will be retained even after power to the device is removed. With these advantages, flash memory has become one of the most widely adopted non-volatile memories for personal computer and electronic equipment.
A typical flash memory has a floating gate and a control gate fabricated using doped polysilicon. To program data into or erase data from a flash memory cell, an appropriate bias voltage is applied to the source region, the drain region and the control gate respectively so that electrons are injected into the floating gate or withdrawn from the floating gate. The most common mode for injecting electrons into a flash memory cell includes the channel hot-electron injection (CHEI) mode and the Fowler-Nordheim tunneling mode. In general, the types of programming and erasing operations carried out on the memory devices depend on the ways the electrons are injected or pulled out.
FIG. 1 is a schematic cross-sectional view showing a single memory cell of a conventional flash memory. The flash memory cell mainly includes an n-type substrate 100, a deep p-type well 102, an n-type well 104, a stacked gate structure 106, an n-type source region 108a, an n-type drain region 108b, a p-type shallow doped region 109, a p-type deep doped region 110 and a conductive plug 112. The deep p-type well 102 is disposed in the substrate 100 and the n-type well 104 is disposed within the deep p-type well 102. The stacked gate structure 106 is disposed on the substrate 100. The stacked gate structure 106 includes a tunneling layer 114, a floating gate 116, a gate dielectric layer 118 and a control gate 120 sequentially stacked over the substrate 100. The n-type source region 108a and the n-type drain region 108b are disposed in the n-type well 104 and the p-type deep doped region 110 on each side of the stacked gate structure 106. The p-type shallow doped region 109 is disposed in the n-type well 104 underneath the stacked gate structure 106. The p-type deep doped region 110 is disposed within the n-type well 104 on one side of the stacked gate structure 106 but adjacent to the p-type shallow doped region 109. The conductive plug 112 in the substrate 100 extends downward to pass through the n-type drain region 108b and connect with a portion of the p-type deep doped region 110.
To program data into the aforementioned flash memory cell, a bias voltage is applied to the source region, the drain region and the control gate respectively. However, the control gate and the source region of the memory cell are also connected to the control gate and the source region of a neighboring memory cell. That is, two memory cells share a common word line and source line. Consequently, a voltage applied to select one particular memory cell may interfere with other non-selected memory cells on the same word line leading to reliability problems in the memory devices.
In addition, the disposition of the control gate and the source region close to each other may increase the probability of having a leaky device when a flash memory cell is programmed.
Furthermore, the aforementioned programming operation may cause the flash memory cell to be over-programmed, thereby leading to subsequent read-out problems. Due to the restriction imposed by the over-programming problems, the operable threshold voltage range of the device is severely compressed. In other words, the flash memory cell is limited to the storage of a single data bit.